Canadian Chip Startups Team up with Taiwan Foundries on Advanced Packaging

Canadian semiconductor developers showed design automation and packaging technologies in Taipei, seeking integration with Taiwan’s high-volume manufacturing lines ahead of SEMICON Taiwan.

The Canada-Taiwan Semiconductor Co-Creation Forum 2026 brought together specialized tech firms offering solutions for bottlenecks in artificial intelligence hardware, hybrid bonding and analog circuit layout.

Targeting packaging bottlenecks

Rather than funding domestic wafer fabrication plants, Canadian firms are positioning themselves upstream in research, design tools and specialized metrology. AsterQuanta presented an AI-driven platform that applies reinforcement learning to automate analog circuit design, a discipline that still depends heavily on manual engineering adjustments.

Digitho introduced programmable photomask software designed to adjust lithography patterns dynamically based on placement offsets of chiplets during heterogeneous integration. The system aims to increase interconnect density by adapting exposure patterns directly on the substrate.

Metrology and vacuum subsystems

In quality control, ICSPI presented micro-scale atomic force microscopy systems built onto one-square-millimetre chips. Operating multiple AFM probes in parallel allows high-throughput, nanoscale surface measurement required for hybrid bonding and advanced copper pad inspection.

Meaglow exhibited hollow-cathode plasma source reactors engineered to reduce oxygen contamination in thin-film nitride layers. Toronto-founded AI processor developer Tenstorrent, which established an operating unit in Taiwan last year, also outlined its RISC-V and neural network processor roadmap.

For Asian foundries and packaging houses facing skilled engineering shortages and tighter hybrid bonding tolerances, adopting specialised toolsets from overseas research hubs provides immediate productivity gains without rebuilding core manufacturing infrastructure.

The participating suppliers now face qualification trials to demonstrate throughput and defect-reduction targets on standard 300mm wafer production lines across Taiwanese contract manufacturers.